Title: SpiNNaker: A low-power approach to supercomputing for neural network simulation

Abstract:
Neural network simulation is a research topic which joins people from various communities, from computer science to neurobiology. The purpose of this is to try to understand how the most complex of the biological neural networks works: the human brain. Some branches of this research use a bottom-up approach: starting from the analysis of brains (either human or animal) they try to capture biological data. These data are then used by scientists to replicate the observed behaviours using models of neural network through simulation hardware/software.

SpiNNaker (a contraction of Spiking Neural Network Architecture) is a million-core computing engine whose flagship goal is to be able to simulate the behaviour of aggregates of up to a billion neurons in real time. It consists of an array of ARM9 cores, communicating via packets carried by a custom interconnect fabric. The packets are small (40 or 72 bits), and their transmission is brokered entirely by hardware through asynchronous channels.

The SpiNNaker engine is a massively-parallel multi-core computing system. It will contain more than 1 million ARM9 cores and 7Tbytes of RAM distributed throughout the system in 50K+ nodes, each node being a System-in-Package (SiP) containing 18 cores plus a 128Mbyte off-die SDRAM. Each core has associated with it 96Kbytes of tightly-coupled memory (TCM).

The physical hierarchy of the system has each node containing two silicon dies - the SpiNNaker chip itself, plus the Mobile DDR (Double Data Rate) SDRAM, which is physically mounted on top of the SpiNNaker die and stitch-bonded to it. The nodes are packaged and mounted in a 48-node hexagonal array on a PCB (Printed Circuit Board), the full system requiring 1,200 such boards. In operation, the engine consumes at most 90kW of electrical power.

The SpiNNaker programming paradigm is a simple, event-driven model. Applications do not control execution flow, they can only indicate the functions, referred to as callbacks; these are executed when specific events occur, such as the arrival of a packet, the completion of a Direct Memory Access (DMA) transfer or the lapse of a periodic time interval. The SpiNNaker Application Run-time Kernel controls the flow of execution and schedules/dispatches application callback functions.

Detailed models of the visual and somatosensory cortices have been simulated using software that accepts anatomical data and configures the hardware accordingly; the hardware has been extended to accept input from neuromorphic sensors that represent environmental cues as biologically-plausible trains of spikes. This talk will present the SpiNNaker hardware, its application to modelling neural circuits, and its use in real-time sensory-motor loops.

More information at: http://apt.cs.man.ac.uk/projects/SpiNNaker/